-- A,B are inputs -- C is output ( A x B ) -- based on IEEE standard -- s <- exponent -> <- mantissa -> -- 64 62 11bits 52 51 52 bits 0 -- written by N.M.Duc 16th June 1997 -- completely tested library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- this statement is needed when complile with Peak tools --use IEEE.std_logic_arith.all; -- this statement is needed when complile with Cadence tools entity MULT is port( A,B :in std_logic_vector(63 downto 0); C :out std_logic_vector(63 downto 0) ); end MULT; architecture RTL of MULT is constant OFFSET : std_logic_vector(11 downto 0):="001111111111"; begin process(A,B) variable Sa,Sb,Sc : std_logic; variable Ea,Eb : std_logic_vector(10 downto 0); variable Ecbuf : std_logic_vector(12 downto 0); variable Ma,Mb,Mc : std_logic_vector(51 downto 0); variable Mmultp : std_logic_vector(105 downto 0); variable Mround : std_logic_vector(54 downto 0); begin Sa := A(63); Sb := B(63); Sc := Sa xor Sb; Ea := A(62 downto 52); Eb := B(62 downto 52); Ecbuf := (("00" & Ea) + ("00" & Eb)) - OFFSET; if( Ecbuf(12)='1' ) then -- Ecbuff's underflow C <= Sc & "00000000000" & "000000000000000000000000000000000000000000"; else Ma := A(51 downto 0); Mb := B(51 downto 0); Mmultp := ( '1' & Ma ) * ( '1' & Mb ); if( Mmultp(105)='1' ) then -- right shift Mmultp 1 bit and increte Ecbuff Mmultp := '0' & Mmultp(105 downto 1); Ecbuf := Ecbuf +1; end if; if( Ecbuf(11)='1' ) then -- Ecbuf's overflow Ecbuf := "0011111111111"; end if; if( Mmultp(51)='1' ) then -- round off Mround := Mmultp(105 downto 51) + 1; else Mround := Mmultp(105 downto 51); end if; if( Mround(54)='1' ) then -- Mround's overflow Mc := Mround(53 downto 2); Ecbuf := Ecbuf +1; else Mc := Mround(52 downto 1); end if; if( Ecbuf(11)='1' ) then -- Ecbuf's overflow Ecbuf := "0011111111111"; end if; C <= Sc & Ecbuf(10 downto 0) & Mc; end if; -- of if(E_c(12)='1') end process; end RTL;