-- A,B are inputs -- C is output ( A x B ) -- based on IEEE standard -- s <- exponent -> <- mantissa -> -- x xxxxx xxxxx xxx xxxx xxxx xxxx xxxx xxxx -- written by N.M.Duc May 1997 -- completely tested library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- this statement is needed when complile with Peak tools --use IEEE.std_logic_arith.all; -- this statement is needed when complile with Cadence tools entity MULT is port( A,B :in std_logic_vector(31 downto 0); C :out std_logic_vector(31 downto 0) ); end MULT; architecture RTL of MULT is constant OFFSET : std_logic_vector(8 downto 0):="001111111"; begin process(A,B) variable Sa,Sb,Sc : std_logic; variable Ea,Eb : std_logic_vector(7 downto 0); variable Ecbuf : std_logic_vector(9 downto 0); variable Ma,Mb,Mc : std_logic_vector(22 downto 0); variable Mmultp : std_logic_vector(47 downto 0); variable Mround : std_logic_vector(25 downto 0); begin Sa := A(31); Sb := B(31); Sc := Sa xor Sb; Ea := A(30 downto 23); Eb := B(30 downto 23); Ecbuf := (("00" & Ea) + ("00" & Eb)) - OFFSET; if( Ecbuf(9)='1' ) then -- Ecbuff's underflow C <= Sc & "00000000" & "00000000000000000000000"; else Ma := A(22 downto 0); Mb := B(22 downto 0); Mmultp := ( '1' & Ma ) * ( '1' & Mb ); if( Mmultp(47)='1' ) then -- right shift Mmultp 1 bit and increte Ecbuff Mmultp := '0' & Mmultp(47 downto 1); Ecbuf := Ecbuf +1; end if; if( Ecbuf(8)='1' ) then -- Ecbuf's overflow Ecbuf := "0011111111"; end if; if( Mmultp(22)='1' ) then -- round off Mround := Mmultp(47 downto 22) + 1; else Mround := Mmultp(47 downto 22); end if; if( Mround(25)='1' ) then -- Mround's overflow Mc := Mround(24 downto 2); Ecbuf := Ecbuf +1; else Mc := Mround(23 downto 1); end if; if( Ecbuf(8)='1' ) then -- Ecbuf's overflow Ecbuf := "0011111111"; end if; C <= Sc & Ecbuf(7 downto 0) & Mc; end if; -- of if(E_c(9)='1') end process; end RTL;