-- 32 bit floating point number divider -- June, 30th 1997 written by N.M.Duc -- uncompletely tested library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- this statement is needed when complile with Peak tools use IEEE.std_logic_arith.all; -- this statement is needed when complile with Cadence tools use work.divider24; -- include 24 bit (integer) divider. entity DIVIDER is port( A,B :in std_logic_vector(31 downto 0); C :out std_logic_vector(31 downto 0) ); end DIVIDER; architecture RTL of DIVIDER is component divider24 port( A : in std_logic_vector(23 downto 0); B : in std_logic_vector(23 downto 0); C : out std_logic_vector(23 downto 0) ); end component; constant OFFSET : std_logic_vector(9 downto 0):="0001111111"; signal Ma,Mb,M_divide : std_logic_vector(23 downto 0); begin con_div : divider24 port map (Ma,Mb,M_divide); div_bod : process(A,B,M_divide) variable Sa,Sb,Sc : std_logic; variable Ea,Eb : std_logic_vector(7 downto 0); variable Ecbuf : std_logic_vector(9 downto 0); variable Mc : std_logic_vector(22 downto 0); begin Sa := A(31); Sb := B(31); Sc := Sa xor Sb; Ea := A(30 downto 23); Eb := B(30 downto 23); Ma <= '1' & A(22 downto 0); Mb <= '1' & B(22 downto 0); Ecbuf := (("00" & Ea) +OFFSET) - ("00" & Eb) ; if( Ecbuf(9)='1' ) then -- Ecbuff's underflow. Set special value(0). C <= Sc & "00000000" & "00000000000000000000000"; elsif( Ecbuf(8)='1' ) then -- Ecbuf's overflow. Set special value(inf.). C <= Sc & "11111111" & "00000000000000000000000"; else -- M_a is always smaller than 2xMb ,because Ma(24)=0 -- while 2xMb(24)=1. Therefore, M_devide cannot be bigger -- or equal 2. With the same reason, M_divide cannot be smaller -- or equal 1/2. -- 1/2 < M_divide < 2 -- This means than there are two cases, -- 1) 1<= M_divide <2 the mantissa is already normalized. -- 2) 1/2