library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FPMULT is
port ( A , B : in std_logic_vector(31 downto 0);
       Q : out std_logic_vector(31 downto 0);
       CLK : in std_logic);
end FPMULT;

architecture RTL of FPMULT is
signal MA,MB : std_logic_vector(23 downto 0);
signal MC,MC0: std_logic_vector(25 downto 0);
signal MQ : std_logic_vector(22 downto 0);
signal EA,EB ,EC0 ,EC1: std_logic_vector(9 downto 0);
signal EC0A,EC1A,EQ : std_logic_vector(7 downto 0);
signal S,SS,SSS,SQ: std_logic;
begin  

 process begin --1st step--
  wait until CLK'event and CLK = '1';
  MA <= "1" & A(22 downto 0); MB <= "1" & B(22 downto 0);
  EA <= "00" & A(30 downto 23); EB <= "00" & B(30 downto 23);
  S <= A(31) xor B(31);
 end process;

 process --2nd step-- 
  variable TMC : std_logic_vector(47 downto 0);
 begin
  wait until CLK'event and CLK = '0';
  SS <= S;
  TMC := MA * MB; MC <= TMC(47 downto 22); 
  if    ( (EA = "0011111111") or (EB = "0011111111") )
  then EC0 <= "0011111111"; EC1 <= "0011111111"; 
  elsif ( (EA = "0000000000") or (EB = "0000000000") )
  then EC0 <= "0000000000"; EC1 <= "0000000000";
  else EC0 <= EA + EB - "0001111111"; EC1 <= EA + EB - "0001111110";
  end if;
 end process; 

 process begin --3rd step--
  wait until CLK'event and CLK = '1';
  SSS <= SS;
  EC0A <= EC1(7 downto 0);EC1A <= EC1(7 downto 0);
  if ( MC(25) = '0' ) then MC0 <= MC + "0000000000000000000000001";    
                      else MC0 <= MC + "0000000000000000000000010";
  end if;
   case EC0(9 downto 8) is
    when "11" => EC0A <= "00000000"; when "01" => EC0A <= "11111111";       
    when others => EC0A <= EC0(7 downto 0); 
   end case;
   case EC1(9 downto 8) is
    when "11" => EC1A <= "00000000"; when "01" => EC1A <= "11111111";       
    when others => EC1A <= EC1(7 downto 0);
   end case;
 end process;

 process begin --4th step--
  wait until CLK'event and CLK = '0';
  SQ <= SSS;
  if ( MC0(25) = '0' ) then MQ <= MC0(23 downto 1); EQ <= EC0A; 
                       else MQ <= MC0(24 downto 2); EQ <= EC1A;
  end if;
 end process;
 Q <= SQ & EQ & MQ;
end RTL;