-- 30th June 1997, written by N.M.Duc
-- 24 bit integer divider

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all; -- include this when use operator +,*,- with
									-- std_logic_vector

entity DIVIDER24 is
    port (
        A: in  std_logic_vector(23 downto 0);
        B: in  std_logic_vector(23 downto 0);
        C: out std_logic_vector(23 downto 0)
        );

end DIVIDER24;

architecture BEHAVIOR of DIVIDER24 is
begin
	div_lab: process (A,B)
	  variable	At,Bt,remain	: std_logic_vector(24 downto 0);
	begin
	  At := '0'&A;  Bt := '0'&B;	    
	  for index in 23 downto 0 loop
	  	remain := At - Bt;
	  	if( remain(24)='1' ) then
	  		C(index) <= '0';
	  		At := At(23 downto 0) & '0';
	  	else
	  		C(index) <= '1';
	  		At := remain(23 downto 0) & '0';
	  	end if;
	  end loop;
	end process;
end BEHAVIOR;