library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FPSQRT is
port (
      signal A   : in  std_logic_vector( 31 downto 0);
      signal Q   : out std_logic_vector( 31 downto 0);
      signal CLK : in  std_logic
     );

end FPSQRT;
architecture RTL of FPSQRT is

begin
process

variable M    : std_logic_vector(24 downto 0);
variable E,ET : std_logic_vector( 7 downto 0 );

variable M0 , S0 , M1T : std_logic_vector(1 downto 0);
variable M1 , S1 , M2T : std_logic_vector(3 downto 0);
variable M2 , S2 , M3T : std_logic_vector(5 downto 0);
variable M3 , S3 , M4T : std_logic_vector(7 downto 0);
variable M4 , S4 , M5T : std_logic_vector(9 downto 0);
variable M5 , S5 , M6T : std_logic_vector(11 downto 0);
variable M6 , S6 , M7T : std_logic_vector(13 downto 0);
variable M7 , S7 , M8T : std_logic_vector(15 downto 0);
variable M8 , S8 , M9T : std_logic_vector(17 downto 0);
variable M9 , S9 , M10T : std_logic_vector(19 downto 0);
variable M10 , S10 , M11T : std_logic_vector(21 downto 0);
variable M11 , S11 , M12T : std_logic_vector(23 downto 0);
variable M12 , S12 , M13T : std_logic_vector(25 downto 0);
variable M13 , S13 , M14T : std_logic_vector(27 downto 0);
variable M14 , S14 , M15T : std_logic_vector(29 downto 0);
variable M15 , S15 , M16T : std_logic_vector(31 downto 0);
variable M16 , S16 , M17T : std_logic_vector(33 downto 0);
variable M17 , S17 , M18T : std_logic_vector(35 downto 0);
variable M18 , S18 , M19T : std_logic_vector(37 downto 0);
variable M19 , S19 , M20T : std_logic_vector(39 downto 0);
variable M20 , S20 , M21T : std_logic_vector(41 downto 0);
variable M21 , S21 , M22T : std_logic_vector(43 downto 0);
variable M22 , S22 , M23T : std_logic_vector(45 downto 0);
variable M23 , S23 , M24T : std_logic_vector(47 downto 0);

variable W1 : std_logic_vector(1 downto 0);
variable W2 : std_logic_vector(2 downto 0);
variable W3 : std_logic_vector(3 downto 0);
variable W4 : std_logic_vector(4 downto 0);
variable W5 : std_logic_vector(5 downto 0);
variable W6 : std_logic_vector(6 downto 0);
variable W7 : std_logic_vector(7 downto 0);
variable W8 : std_logic_vector(8 downto 0);
variable W9 : std_logic_vector(9 downto 0);
variable W10 : std_logic_vector(10 downto 0);
variable W11 : std_logic_vector(11 downto 0);
variable W12 : std_logic_vector(12 downto 0);
variable W13 : std_logic_vector(13 downto 0);
variable W14 : std_logic_vector(14 downto 0);
variable W15 : std_logic_vector(15 downto 0);
variable W16 : std_logic_vector(16 downto 0);
variable W17 : std_logic_vector(17 downto 0);
variable W18 : std_logic_vector(18 downto 0);
variable W19 : std_logic_vector(19 downto 0);
variable W20 : std_logic_vector(20 downto 0);
variable W21 : std_logic_vector(21 downto 0);
variable W22 : std_logic_vector(22 downto 0);
variable W23 : std_logic_vector(23 downto 0);



begin

wait until CLK'event and CLK = '1';

-- とっとと 指数部を計算する
ET :=  A(30 downto 23) - "01111111";
E :=  ('0' & ET(7 downto 1)) + "01111111"; 


-- ここでは ２bit 毎に計算されるよう bit シフトしている
if ( A(23) = '1' )
  then  M := "01" & A(22 downto 0);
  else M := '1'  & A(22 downto 0) & '0';
end if;



M0 := M(24 downto 23);
W1 := "10";
M1 := (M0 - "01") & M(22 downto 21);


S1 := M1 - ('0' & W1 & '1');
if ( S1(S1'HIGH) = '0' )
then M2T := S1;
else M2T := M1;
end if;
W2 := ( W1 & not S1(S1'HIGH) ) + ( "00" & not S1(S1'HIGH) );
M2 := M2T & M(20 downto 19) ;
 
S2 := M2 - ('0' & W2 & '1');
if ( S2(S2'HIGH) = '0' )
then M3T := S2;
else M3T := M2;
end if;
W3 := ( W2 & not S2(S2'HIGH) ) + ( "000" & not S2(S2'HIGH) );
M3 := M3T & M(18 downto 17) ;

S3 := M3 - ('0' & W3 & '1');
if ( S3(S3'HIGH) = '0' )
then M4T := S3;
else M4T := M3;
end if;
W4 := ( W3 & not S3(S3'HIGH) ) + ( "0000" & not S3(S3'HIGH) );
M4 := M4T & M(16 downto 15);
S4 := M4 - ('0' & W4 & '1');
if ( S4(S4'HIGH) = '0' )
then M5T := S4;
else M5T := M4;
end if;
W5 := ( W4 & not S4(S4'HIGH) ) + ( "00000" & not S4(S4'HIGH) );
M5 := M5T & M(14 downto 13);

S5 := M5 - ('0' & W5 & '1');
if ( S5(S5'HIGH) = '0' )
then M6T := S5;
else M6T := M5;
end if;
W6 := ( W5 & not S5(S5'HIGH) ) + ( "000000" & not S5(S5'HIGH) );
M6 := M6T & M(12 downto 11);

S6 := M6 - ('0' & W6 & '1');
if ( S6(S6'HIGH) = '0' )
then M7T := S6;
else M7T := M6;
end if;
W7 := ( W6 & not S6(S6'HIGH) ) + ( "0000000" & not S6(S6'HIGH) );
M7 := M7T & M(10 downto 9);

S7 := M7 - ('0' & W7 & '1');
if ( S7(S7'HIGH) = '0' )
then M8T := S7;
else M8T := M7;
end if;
W8 := ( W7 & not S7(S7'HIGH) ) + ( "00000000" & not S7(S7'HIGH) );
M8 := M8T & M(8 downto 7);

S8 := M8 - ('0' & W8 & '1');
if ( S8(S8'HIGH) = '0' )
then M9T := S8;
else M9T := M8;
end if;
W9 := ( W8 & not S8(S8'HIGH) ) + ( "000000000" & not S8(S8'HIGH) );
M9 := M9T & M(6 downto 5);

S9 := M9 - ('0' & W9 & '1');
if ( S9(S9'HIGH) = '0' )
then M10T := S9;
else M10T := M9;
end if;
W10 := ( W9 & not S9(S9'HIGH) ) + ( "0000000000" & not S9(S9'HIGH) );
M10 := M10T & M(4 downto 3);

S10 := M10 - ('0' & W10 & '1');
if ( S10(S10'HIGH) = '0' )
then M11T := S10;
else M11T := M10;
end if;
W11 := ( W10 & not S10(S10'HIGH) ) + ( "00000000000" & not S10(S10'HIGH) );
M11 := M11T & M(2 downto 1);

S11 := M11 - ('0' & W11 & '1');
if ( S11(S11'HIGH) = '0' )
then M12T := S11;
else M12T := M11;
end if;
W12 := ( W11 & not S11(S11'HIGH) ) + ( "000000000000" & not S11(S11'HIGH) );
M12 := M12T & M(0) & '0';

S12 := M12 - ('0' & W12 & '1');
if ( S12(S12'HIGH) = '0' )
then M13T := S12;
else M13T := M12;
end if;
W13 := ( W12 & not S12(S12'HIGH) ) + ( "0000000000000" & not S12(S12'HIGH) );
M13 := M13T & "00";

S13 := M13 - ('0' & W13 & '1');
if ( S13(S13'HIGH) = '0' )
then M14T := S13;
else M14T := M13;
end if;
W14 := ( W13 & not S13(S13'HIGH) ) + ( "00000000000000" & not S13(S13'HIGH) );
M14 := M14T & "00";
S14 := M14 - ('0' & W14 & '1');
if ( S14(S14'HIGH) = '0' )
then M15T := S14;
else M15T := M14;
end if;
W15 := ( W14 & not S14(S14'HIGH) ) + ( "000000000000000" & not S14(S14'HIGH) );
M15 := M15T & M(14 downto 13);

S15 := M15 - ('0' & W15 & '1');
if ( S15(S15'HIGH) = '0' )
then M16T := S15;
else M16T := M15;
end if;
W16 := ( W15 & not S15(S15'HIGH) ) + ( "0000000000000000" & not S15(S15'HIGH) );
M16 := M16T & "00";

S16 := M16 - ('0' & W16 & '1');
if ( S16(S16'HIGH) = '0' )
then M17T := S16;
else M17T := M16;
end if;
W17 := ( W16 & not S16(S16'HIGH) ) + ( "00000000000000000" & not S16(S16'HIGH) );
M17 := M17T & "00";

S17 := M17 - ('0' & W17 & '1');
if ( S17(S17'HIGH) = '0' )
then M18T := S17;
else M18T := M17;
end if;
W18 := ( W17 & not S17(S17'HIGH) ) + ( "000000000000000000" & not S17(S17'HIGH) );
M18 := M18T & "00";

S18 := M18 - ('0' & W18 & '1');
if ( S18(S18'HIGH) = '0' )
then M19T := S18;
else M19T := M18;
end if;
W19 := ( W18 & not S18(S18'HIGH) ) + ( "0000000000000000000" & not S18(S18'HIGH) );
M19 := M19T & "00";

S19 := M19 - ('0' & W19 & '1');
if ( S19(S19'HIGH) = '0' )
then M20T := S19;
else M20T := M19;
end if;
W20 := ( W19 & not S19(S19'HIGH) ) + ( "00000000000000000000" & not S19(S19'HIGH) );

M20 := M20T & "00";

S20 := M20 - ('0' & W20 & '1');
if ( S20(S20'HIGH) = '0' )
then M21T := S20;
else M21T := M20;
end if;
W21 := ( W20 & not S20(S20'HIGH) ) + ( "000000000000000000000" & not S20(S20'HIGH) );
M21 := M21T & "00";

S21 := M21 - ('0' & W21 & '1');
if ( S21(S21'HIGH) = '0' )
then M22T := S21;
else M22T := M21;
end if;
W22 := ( W21 & not S21(S21'HIGH) ) + ( "0000000000000000000000" & not S21(S21'HIGH) );
M22 := M22T & "00";

S22 := M22 - ('0' & W22 & '1');
if ( S22(S22'HIGH) = '0' )
then M23T := S22;
else M23T := M22;
end if;
W23 := ( W22 & not S22(S22'HIGH) ) + ( "00000000000000000000000" & not S22(S22'HIGH) );
M23 := M23T & "00";

S23 := M23 - ('0' & W23 & '1');


Q <= '0' & E  
   & not S1(S1'HIGH) & not S2(S2'HIGH)  & not S3(S3'HIGH)  & not S4(S4'HIGH) 
   & not S5(S5'HIGH) & not S6(S6'HIGH)  & not S7(S7'HIGH)  & not S8(S8'HIGH)   
   & not S9(S9'HIGH) & not S10(S10'HIGH)  & not S11(S11'HIGH)  & not S12(S12'HIGH)   
   & not S13(S13'HIGH) & not S14(S14'HIGH)  & not S15(S15'HIGH)  & not S16(S16'HIGH)   
   & not S17(S17'HIGH) & not S18(S18'HIGH)  & not S19(S19'HIGH)  & not S20(S20'HIGH)   
   & not S21(S21'HIGH) & not S22(S22'HIGH)  & not S23(S23'HIGH);   
               

end process;


end RTL;